In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces. The features and spaces are patterned so as to form devices, such as transistors, capacitors and resistors. These devices are then interconnected to achieve a desired electrical function, forming an integrated circuit (IC). The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, and etching. Such techniques are described in S. M. Sze, VLSI Technology, 2nd ed., New York, McGraw-Hill, 1988, which is herein incorporated by reference for all purposes.
The demand to further miniaturize ICs have resulted in features and spaces that are smaller and more closely packed to increase device density per unit area on the substrate. However, dimension of the features and spaces depends on the resolution capability of the lithographic system. This is referred to as the minimum feature size (F) or groundrule (GR).
Lithography for patterning the substrate to create features typically includes depositing a layer of photoresist on the surface of the substrate. An exposure source generating, for example, deep ultra-violet (DUV) radiation illuminates a mask containing the desired pattern. The illumination creates an image of the mask which is projected or printed on the substrate surface, selectively exposing the photoresist layer with DUV radiation. Depending on whether a positive or negative resist is used, either the exposed or unexposed portions of the resist layer are removed during development to selectively expose regions of the substrates below. The exposed regions are then patterned or etched by, for example, reactive ion etching (RIE) to create the features and spaces. Thus, the feature size is limited by the wavelength of the exposure source to create the mask image and the preciseness of the optical system that projects that image onto the resist layer.
To increase density or to extend the technology beyond that capable of current lithographic systems, there is a need to create features and spaces that are smaller than F or GR.
As an example, metal lines are used to electrically interconnect devices of an IC together. Metal lines are generally made either by 1) depositing a layer of metal on a semiconductor substrate, depositing a photoresist over the metal, and patterning the photoresist to form openings over the metal layer, and etching away the metal in the openings; or 2) forming openings or trenches in a substrate using photolithography and depositing metal in the openings. Excess metal can be removed by planarizing, either with an etchant or by chemical metal polishing techniques, to remove the excess metal down to the surface of the substrate.
To increase the density of the IC, smaller features such as the metal lines are required. Although one way of decreasing the feature size is to migrate to a more advanced lithographic system capable of producing smaller F, this requires significant capital expenditures. Moreover, the more advanced lithographic systems may not be feasible in a manufacturing setting as they increase raw process time or the materials associated with their use, such as resist, are very expensive.
Thus from the foregoing discussion, it is desirable to be able to produce sub-GR features.